A magnetic random access memory (MRAM) device is generally comprised of an array of parallel first conductive lines on a horizontal plane, an array of parallel second conductive lines on a second horizontal plane spaced above and formed in a direction perpendicular to the first conductive lines, and a magnetic tunnel junction (MTJ) formed at each location where a second conductive line crosses over a first conductive line. A first conductive line may be a word line while a second conductive line is a bit line or vice versa. Alternatively, the first conductive line may be a sectioned line which is a bottom electrode. There are typically other devices including transistors and diodes below the array of first conductive lines and at least one additional conductive layer comprised of an array of second word lines or second bit lines above the array of second conductive lines.
The MTJ consists of a stack of layers with a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. One of the ferromagnetic layers is a pinned layer in which the magnetization (magnetic moment) direction is fixed by exchange coupling with an adjacent anti-ferromagnetic (AFM) pinning layer. The second ferromagnetic layer is a free layer in which the magnetization direction can be changed by external magnetic fields. The magnetization direction of the free layer may change in response to external magnetic fields which can be generated by passing currents through the conductive lines. When the magnetization direction of the free layer is parallel to that of the pinned layer, there is a lower resistance for tunneling current across the dielectric layer than when the magnetization directions of the free and pinned layers are anti-parallel. The MTJ stores information as a result of having one of two different magnetic states.
In a read operation, the information is read by sensing the magnetic state (resistance level) of the MTJ through a sensing current flowing through the MTJ, typically in a current perpendicular to plane (CPP) configuration. During a write operation, the information is written to the MTJ by changing the magnetic state to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents.
Referring to FIG. 1, a conventional MRAM device 1 comprised of two adjacent MRAM cells with two MTJs 4 is depicted. There is a substrate 2 with a first conductive layer that in this example includes bottom electrodes 3 formed therein. Each bottom electrode 3 contacts an overlying MTJ 4 which is enclosed on the sides by an insulation layer 5. In this example, there is a bit line 6 in a second conductive layer that contacts the top of the MTJs 4. Typically, a second insulation layer 7 is deposited on the second conductive layer including bit line 6. A third conductive layer 9 which may be an array of word lines is formed within a third insulation layer 8 on the second insulation layer 7. There are other circuits such as circuits in a peripheral area that are used to select certain MTJs for read or write operations.
Referring to FIG. 2, a typical MTJ 4 is shown which is a stack of layers including one or more bottom seed layers 10 such as NiFeCr formed on a bottom electrode 3. Next, an anti-ferromagnetic (AFM) pinning layer 11 that may be PtMn, for example, is deposited on the seed layer 10. There is a ferromagnetic “pinned” layer 12 on the AFM layer 11 that may be a composite of multiple layers including CoFe layers. The tunnel barrier layer 13 above the pinned layer 12 is generally comprised of a dielectric material such as Al2O3. Above the tunnel barrier layer 13 is a ferromagnetic “free” layer 14 which may be another composite layer that includes NiFe, for example. At the top of the MTJ stack is one or more cap layers 15. In configurations where only one cap layer is employed, the cap layer 15 is comprised of conductive material such as Ta for making an electrical contact to the subsequently formed bit line 6. When two cap layers are used, the top cap layer is a conductive layer. This MTJ stack has a so-called bottom spin valve configuration. Alternatively, an MTJ stack may have a top spin valve configuration in which a free layer is formed on a seed layer followed by sequentially forming a tunnel barrier layer, a pinned layer, an AFM layer, and a cap layer.
Referring to FIG. 3, the MTJs 4 are comprised of a cap layer 15 and a composite layer 4a that represents the remaining layers in the MTJ stack. A conventional fabrication process involves stripping the mask (not shown) used for patterning the MTJ stack and then depositing an insulation layer 5 such as silicon oxide or Al2O3 which covers the MTJs. Note that the deposition forms an uneven insulation layer 5 in which the surface region 16 above the cap layer 15 is at a higher level than the surface region 17 not directly above the cap layer. When fabricating high density MRAM chips, it is desirable to have essentially flat topography after each layer is finished. A CMP process is preferred for planarizing the insulation layer 5 so that the top surface of the cap layer 15 is exposed as an electrical contact point for a subsequent second conductive layer.
Referring to FIG. 4, the insulation layer 5, adjacent cap layer 15, and composite layer 4a are shown after the CMP process is complete. Unfortunately, two major issues lead to a degradation of device performance. First, the cap layer 15 has a significant thickness loss during the polishing process. As a result, the cap layer 15 which initially has a thickness t1 is eroded and the thickness loss t2 typically varies across a wafer and from wafer to wafer due to CMP process nonuniformity and other variations. Thus, the distance (t1−t2) between a subsequently formed bit line (not shown) and the free layer which is at the top of the composite layer 4a varies significantly and cannot be adequately controlled. Because the magnetic field strength generated by the bit line or word line current at the free layer strongly depends on the distance (t1−t2), the inability to control this parameter directly translates to a failure to control the switching magnetic field at the free layer and thereby leads to poor device performance.
A second problem is that the CMP process often forms an MTJ 4 that protrudes above the surrounding insulation layer 5 by a distance d. The protrusion distance d varies across a wafer and from wafer to wafer because of the same nonuniformities mentioned previously. The magnitude of d is often larger than 400 Angstroms and in some cases may be similar or larger than the entire thickness of the MTJ stack. Although the thickness of the capping layer 15 can be increased to compensate for CMP process variations, a better method is needed to controllably form a more planar insulation layer 5 with less cap layer thickness loss.
In U.S. Pat. No. 6,384,482, a method for fabricating a uniform dielectric layer is described that involves depositing a first etch stop layer on a raised metal pattern followed by depositing a dielectric layer and then a second etch stop layer on the dielectric layer. The etch stop layers have a lower polish rate than an oxide dielectric layer in a CMP process and prevent erosion on the top surface of the metal pattern.
A method is disclosed for a CMP process involving an MRAM cell in U.S. Pat. No. 6,673,675 in which a WN or TaN layer is used as a cap layer on an MTJ and also functions as a series resistor or as a CMP stop layer. Other materials such as oxides, nitrides, or amorphous carbon may be used as a CMP stop layer.
In U.S. Pat. No. 6,174,737, MTJs are formed on a planar conductive layer. A dielectric layer is deposited on the MTJs and is etched to define holes to the MTJs. A second conductive layer is deposited in the holes to form conductive lines.
A method for forming an MTJ stack is disclosed in U.S. Pat. No. 6,649,953 in which a second insulation layer is formed on an MTJ without a cap layer. The second insulation layer is planarized to expose the top surface of the free layer before a bit line is formed on the free layer. However, the planarization method is not described.